FIG. 1 is a cross-sectional view of a general semiconductor device having a self-alignment contact pad. Referring to FIG. 1, an isolation layer 12, which defines an active region, is formed in a predetermined region on a semiconductor substrate 10 through a general shallow trench isolation (STI) method. Next, a gate electrode 18 is formed on a predetermined portion of the semiconductor substrate 10 having an active region and the isolation layer 12. The gate electrode 18 can be formed by depositing a gate insulating layer 14, a conductive layer 15, a capping layer 16, and a spacer 17 which is formed along the sidewalls of the gate insulating layer 14, the conductive layer 15 and the capping layer 16, on the semiconductor substrate 10. Thereafter, a junction region 20 is formed by implanting impurities into the active region on both sides of the gate electrode 18. A contact pad 22 is formed in a self-aligned manner between the gate electrode 18 and another gate electrode to contact the junction region 20, and an interlevel insulating layer 24 is then formed on the resultant structure. A photoresist pattern exposing the contact pad 22 is formed through a conventional photolithography process on the upper surface of the interlevel insulating layer 24. A contact hole 26 is obtained by etching the exposed interlevel insulating layer 24 using the photoresist pattern as a mask. A conductive layer is then formed on the exposed contact pad 22.
As integrated circuit memory devices are made more highly integrated, the widths of the metal wirings and contact pads generally decrease in proportion to the increase in integration. Decreased widths of the metal wiring and contact pads can considerably increase the difficulty of forming a properly aligned contact hole therewith. Moreover, small contact hole areas can be difficult to fill with a conductive layer and a void may occur in the contact hole. Example misalignment of a contact hole in the interlevel insulating layer is shown in FIG. 1 by the dotted lines 28.